Design of a register renaming unit

Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Register renaming is often used to improve performance in many high-ILP processors. However, there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages34-37
Number of pages4
ISBN (Print)0769501044
StatePublished - 1999
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: Mar 4 1999Mar 6 1999

Other

OtherProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period3/4/993/6/99

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Design of a register renaming unit'. Together they form a unique fingerprint.

  • Cite this

    Bishop, B., Kelliher, T. P., & Irwin, M. J. (1999). Design of a register renaming unit. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 34-37). IEEE.