The use of residue number system (RNS) arithmetic to designing high-speed special-purpose digital hardware that is suitable for VLSI implementation is considered. A processor architecture based on serial-by-modulus (SBM) RNS arithmetic is presented. Although slower in speed, SBM-RNS architectures are conservative in terms of silicon area and provide a mechanism for realizing high-precision signal processors in VLSI circuits of relatively short wordlength.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||4|
|State||Published - Dec 1 1987|
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