Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure

Shengxi Huang; Ximeng Guan; Jinyu Zhang; Victor Moroz; Yan Wang; Zhiping Yu

doi:10.1109/EDSSC.2010.5713687

Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure

Shengxi Huang, Ximeng Guan, Jinyu Zhang, Victor Moroz, Yan Wang, Zhiping Yu

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.

Original language	English (US)
Title of host publication	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
DOIs	https://doi.org/10.1109/EDSSC.2010.5713687
State	Published - Dec 1 2010
Event	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 - Hong Kong, China Duration: Dec 15 2010 → Dec 17 2010

Publication series

Name	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

Other

Other	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
Country	China
City	Hong Kong
Period	12/15/10 → 12/17/10

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2010.5713687

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Huang, S., Guan, X., Zhang, J., Moroz, V., Wang, Y., & Yu, Z. (2010). Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 [5713687] (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). https://doi.org/10.1109/EDSSC.2010.5713687

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abstract = "With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.",

author = "Shengxi Huang and Ximeng Guan and Jinyu Zhang and Victor Moroz and Yan Wang and Zhiping Yu",

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Huang, S, Guan, X, Zhang, J, Moroz, V, Wang, Y & Yu, Z 2010, Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure. in 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010., 5713687, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010, Hong Kong, China, 12/15/10. https://doi.org/10.1109/EDSSC.2010.5713687

Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure. / Huang, Shengxi; Guan, Ximeng; Zhang, Jinyu; Moroz, Victor; Wang, Yan; Yu, Zhiping.

2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. 2010. 5713687 (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Huang, Shengxi

AU - Guan, Ximeng

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AU - Moroz, Victor

AU - Wang, Yan

AU - Yu, Zhiping

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N2 - With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.

AB - With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.

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BT - 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

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Huang S, Guan X, Zhang J, Moroz V, Wang Y, Yu Z. Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. 2010. 5713687. (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). https://doi.org/10.1109/EDSSC.2010.5713687