Abstract
With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.
| Original language | English (US) |
|---|---|
| Title of host publication | 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 |
| DOIs | |
| State | Published - Dec 1 2010 |
| Event | 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 - Hong Kong, China Duration: Dec 15 2010 → Dec 17 2010 |
Publication series
| Name | 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 |
|---|
Other
| Other | 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 |
|---|---|
| Country | China |
| City | Hong Kong |
| Period | 12/15/10 → 12/17/10 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure. / Huang, Shengxi; Guan, Ximeng; Zhang, Jinyu; Moroz, Victor; Wang, Yan; Yu, Zhiping.
2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. 2010. 5713687 (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Design of complementary GAA-NW tunneling-FETs of axial Si-Ge heterostructure
AU - Huang, Shengxi
AU - Guan, Ximeng
AU - Zhang, Jinyu
AU - Moroz, Victor
AU - Wang, Yan
AU - Yu, Zhiping
PY - 2010/12/1
Y1 - 2010/12/1
N2 - With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.
AB - With sub-16nm CMOS nodes looming, this work proposes a novel device structure for Gate-Ail-Around (GAA), Nanowire (NW) tunneling-FET (tFET), with axial heterojunction on the source-channel junction, gate-underlap on the drain end of the channel, and optimized doping levels of source and drain. This structure successfully suppresses the undesirable am bipolar transfer characteristics of conventional tFETs, while maintaining the advantage of small subthreshold swing of less than 60mV/dec. For the first time, an all-tFET inverter is demonstrated to exhibit excellent switching behaviors, outperforming both the homojunction Si NW-tFET and the conventional CMOS in inverters with the same gate length and supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=79952518087&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79952518087&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2010.5713687
DO - 10.1109/EDSSC.2010.5713687
M3 - Conference contribution
AN - SCOPUS:79952518087
SN - 9781424499977
T3 - 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
BT - 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
ER -