We present a design for a charge recovery databus. Previous works have laid the groundwork for our design, presenting the theory that would make adiabatic circuit techniques useful. During a shorting period, the charge is transferred from the falling bit-lines to precharge the rising bit-lines while both the sender and the receiver are off. We simulate this 8-bit charge recovery bus with data based on realistic benchmarks. The power savings average 20% over typical on-chip and off-chip bus capacitances. The savings increase with larger bus capacitances and longer shorting times. The overhead of the control circuitry is estimated at 3.6% of the total power consumption.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - Jan 1 2000|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering