Design of databus charge recovery mechanism

Victor Lyuboslavsky, Benjamin Bishop, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

We present a design for a charge recovery databus. Previous works have laid the groundwork for our design, presenting the theory that would make adiabatic circuit techniques useful. During a shorting period, the charge is transferred from the falling bit-lines to precharge the rising bit-lines while both the sender and the receiver are off. We simulate this 8-bit charge recovery bus with data based on realistic benchmarks. The power savings average 20% over typical on-chip and off-chip bus capacitances. The savings increase with larger bus capacitances and longer shorting times. The overhead of the control circuitry is estimated at 3.6% of the total power consumption.

Original languageEnglish (US)
Pages (from-to)283-287
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - Jan 1 2000

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Recovery
Capacitance
Electric power utilization
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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Design of databus charge recovery mechanism. / Lyuboslavsky, Victor; Bishop, Benjamin; Narayanan, Vijaykrishnan; Irwin, Mary Jane.

In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 01.01.2000, p. 283-287.

Research output: Contribution to journalArticle

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