Design of power-aware FPGA fabrics

Aman Gayasen, Suresh Srinivasan, Vijaykrishnan Narayanan, Mahmut Kandemir

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61% across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.

Original languageEnglish (US)
Pages (from-to)52-64
Number of pages13
JournalInternational Journal of Embedded Systems
Volume3
Issue number1-2
DOIs
StatePublished - Dec 1 2007

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Static random access storage
Field programmable gate arrays (FPGA)
Electric power utilization
Data storage equipment
Electric potential

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

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Design of power-aware FPGA fabrics. / Gayasen, Aman; Srinivasan, Suresh; Narayanan, Vijaykrishnan; Kandemir, Mahmut.

In: International Journal of Embedded Systems, Vol. 3, No. 1-2, 01.12.2007, p. 52-64.

Research output: Contribution to journalArticle

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