Abstract
We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61% across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 52-64 |
| Number of pages | 13 |
| Journal | International Journal of Embedded Systems |
| Volume | 3 |
| Issue number | 1-2 |
| DOIs | |
| State | Published - Dec 1 2007 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
Cite this
}
Design of power-aware FPGA fabrics. / Gayasen, Aman; Srinivasan, Suresh; Narayanan, Vijaykrishnan; Kandemir, Mahmut.
In: International Journal of Embedded Systems, Vol. 3, No. 1-2, 01.12.2007, p. 52-64.Research output: Contribution to journal › Article
TY - JOUR
T1 - Design of power-aware FPGA fabrics
AU - Gayasen, Aman
AU - Srinivasan, Suresh
AU - Narayanan, Vijaykrishnan
AU - Kandemir, Mahmut
PY - 2007/12/1
Y1 - 2007/12/1
N2 - We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61% across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.
AB - We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61% across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.
UR - http://www.scopus.com/inward/record.url?scp=56349105094&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=56349105094&partnerID=8YFLogxK
U2 - 10.1504/IJES.2007.016033
DO - 10.1504/IJES.2007.016033
M3 - Article
VL - 3
SP - 52
EP - 64
JO - International Journal of Embedded Systems
JF - International Journal of Embedded Systems
SN - 1741-1068
IS - 1-2
ER -