Design of residue number system arithmetic units for a VLSI adaptive equalizer

Inseop Lee, William Kenneth Jenkins

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Scopus citations

    Abstract

    This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and an update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper.

    Original languageEnglish (US)
    Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
    EditorsM.A. Bayoumi, G. Jullien
    Pages179-184
    Number of pages6
    DOIs
    StatePublished - Jan 1 1998
    EventProceedings of the 1998 8th Great Lakes Symposium on VLSI - Lafayette, LA, USA
    Duration: Feb 19 1998Feb 21 1998

    Publication series

    NameProceedings of the IEEE Great Lakes Symposium on VLSI
    ISSN (Print)1066-1395

    Other

    OtherProceedings of the 1998 8th Great Lakes Symposium on VLSI
    CityLafayette, LA, USA
    Period2/19/982/21/98

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering

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  • Cite this

    Lee, I., & Jenkins, W. K. (1998). Design of residue number system arithmetic units for a VLSI adaptive equalizer. In M. A. Bayoumi, & G. Jullien (Eds.), Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 179-184). (Proceedings of the IEEE Great Lakes Symposium on VLSI). https://doi.org/10.1109/GLSV.1998.665222