Design Space Exploration for Selector Diode-STTRAM Crossbar Arrays

We report a simulation-based study to understand the integration potential of selector diode (SD) with spin-transfer torque random access memory (STTRAM). SD based on metal-insulator-insulator-metal diode is considered due to features such as high-speed operation, ability to engineer dielectric interfaces and electrode barriers for low VT and bidirectional switching, and immunity to the temperature (due to its tunnel-based conduction). The intended asymmetry in diode I - V behavior provides better sense margin for larger arrays. We describe design challenges and propose device-circuit co-optimization and novel techniques, e.g., write voltage biasing and series/parallel connected SD for robustness and retention. This is the first effort toward solving the design challenges to enable diode-STTRAM crossbar. The proposed structure can enable 3-D stacking of magnetic tunnel junction for densities beyond 4F².