Design space exploration of workload-specific last-level caches

Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Leakage power of last-level caches constitute a significant part of overall power consumption. Various circuit-level and technology-based methods have been proposed to reduce cache leakage. However, from a system designer's perspective, for a particular configuration and workload, it is not clear which method will be most effective. In this work, we make a detailed evaluation and comparison of cache energy reduction techniques. Our results show that when energy is very scarce and important, the best results are obtained with highly energy efficient Tunnel-FET caches. When the available energy increases and performance becomes a bigger concern, there is no single winner. While a small number of capacity sensitive workloads benefit from increased capacity of STT-RAM caches, latency sensitive workloads prefer solutions with smaller latency penalties such as drowsy caches.

Original languageEnglish (US)
Title of host publicationISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages243-248
Number of pages6
DOIs
StatePublished - 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: Jul 30 2012Aug 1 2012

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period7/30/128/1/12

Fingerprint

Random access storage
Field effect transistors
Tunnels
Electric power utilization
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Swaminathan, K., Kultursay, E., Saripalli, V., Narayanan, V., & Kandemir, M. (2012). Design space exploration of workload-specific last-level caches. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design (pp. 243-248) https://doi.org/10.1145/2333660.2333718
Swaminathan, Karthik ; Kultursay, Emre ; Saripalli, Vinay ; Narayanan, Vijaykrishnan ; Kandemir, Mahmut. / Design space exploration of workload-specific last-level caches. ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. pp. 243-248
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Swaminathan, K, Kultursay, E, Saripalli, V, Narayanan, V & Kandemir, M 2012, Design space exploration of workload-specific last-level caches. in ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. pp. 243-248, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, United States, 7/30/12. https://doi.org/10.1145/2333660.2333718

Design space exploration of workload-specific last-level caches. / Swaminathan, Karthik; Kultursay, Emre; Saripalli, Vinay; Narayanan, Vijaykrishnan; Kandemir, Mahmut.

ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 243-248.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir M. Design space exploration of workload-specific last-level caches. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 243-248 https://doi.org/10.1145/2333660.2333718