Abstract
Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network- on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to mini- mize the energy consumption of NoC without violating the pre- specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline| the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-effciency, while meeting the deadlines for all packets.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 50th Annual Design Automation Conference, DAC 2013 |
| DOIs | |
| State | Published - Jul 12 2013 |
| Event | 50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States Duration: May 29 2013 → Jun 7 2013 |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| ISSN (Print) | 0738-100X |
Other
| Other | 50th Annual Design Automation Conference, DAC 2013 |
|---|---|
| Country | United States |
| City | Austin, TX |
| Period | 5/29/13 → 6/7/13 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation
Cite this
}
Designing energy-efficient NoC for real-time embedded systems through slack optimization. / Zhan, Jia; Stoimenov, Nikolay; Ouyang, Jin; Thieley, Lothar; Narayanan, Vijaykrishnan; Xie, Yuan.
Proceedings of the 50th Annual Design Automation Conference, DAC 2013. 2013. 37 (Proceedings - Design Automation Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Designing energy-efficient NoC for real-time embedded systems through slack optimization
AU - Zhan, Jia
AU - Stoimenov, Nikolay
AU - Ouyang, Jin
AU - Thieley, Lothar
AU - Narayanan, Vijaykrishnan
AU - Xie, Yuan
PY - 2013/7/12
Y1 - 2013/7/12
N2 - Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network- on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to mini- mize the energy consumption of NoC without violating the pre- specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline| the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-effciency, while meeting the deadlines for all packets.
AB - Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network- on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to mini- mize the energy consumption of NoC without violating the pre- specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline| the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-effciency, while meeting the deadlines for all packets.
UR - http://www.scopus.com/inward/record.url?scp=84879847596&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84879847596&partnerID=8YFLogxK
U2 - 10.1145/2463209.2488780
DO - 10.1145/2463209.2488780
M3 - Conference contribution
AN - SCOPUS:84879847596
SN - 9781450320719
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 50th Annual Design Automation Conference, DAC 2013
ER -