Designing leakage aware multipliers

M. DeRenzo, M. J. Irwin, Vijaykrishnan Narayanan

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. Hence, the design of leakage-conscious memory and data path components is vital. This paper focuses on designing a 32-bit double precision multiplier, and snows haw the appropriate choice of implementation primitives used in the design can provide significant leakage energy savings without much impact on performance.

Original languageEnglish (US)
Pages (from-to)654-657
Number of pages4
JournalProceedings of the IEEE International Conference on VLSI Design
Volume17
StatePublished - 2004

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Limiters
Snow
Threshold voltage
Energy conservation
Electric power utilization
Energy utilization
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{f3a68f32bf9a418b8b624b1fdc63540c,
title = "Designing leakage aware multipliers",
abstract = "Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. Hence, the design of leakage-conscious memory and data path components is vital. This paper focuses on designing a 32-bit double precision multiplier, and snows haw the appropriate choice of implementation primitives used in the design can provide significant leakage energy savings without much impact on performance.",
author = "M. DeRenzo and Irwin, {M. J.} and Vijaykrishnan Narayanan",
year = "2004",
language = "English (US)",
volume = "17",
pages = "654--657",
journal = "Proceedings of the IEEE International Conference on VLSI Design",
issn = "1063-9667",
publisher = "IEEE Computer Society",

}

Designing leakage aware multipliers. / DeRenzo, M.; Irwin, M. J.; Narayanan, Vijaykrishnan.

In: Proceedings of the IEEE International Conference on VLSI Design, Vol. 17, 2004, p. 654-657.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Designing leakage aware multipliers

AU - DeRenzo, M.

AU - Irwin, M. J.

AU - Narayanan, Vijaykrishnan

PY - 2004

Y1 - 2004

N2 - Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. Hence, the design of leakage-conscious memory and data path components is vital. This paper focuses on designing a 32-bit double precision multiplier, and snows haw the appropriate choice of implementation primitives used in the design can provide significant leakage energy savings without much impact on performance.

AB - Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. Hence, the design of leakage-conscious memory and data path components is vital. This paper focuses on designing a 32-bit double precision multiplier, and snows haw the appropriate choice of implementation primitives used in the design can provide significant leakage energy savings without much impact on performance.

UR - http://www.scopus.com/inward/record.url?scp=2342533025&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2342533025&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:2342533025

VL - 17

SP - 654

EP - 657

JO - Proceedings of the IEEE International Conference on VLSI Design

JF - Proceedings of the IEEE International Conference on VLSI Design

SN - 1063-9667

ER -