Detecting SEU-caused routing errors in SRAM-based FPGAs

E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Conference on VLSI Design
Pages736-741
Number of pages6
DOIs
StatePublished - Dec 1 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
CountryIndia
CityKolkata
Period1/3/051/7/05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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