TY - GEN
T1 - Detecting SEU-caused routing errors in SRAM-based FPGAs
AU - Reddy, E. Syam Sundar
AU - Chandrasekhar, Vikram
AU - Sashikanth, M.
AU - Kamakoti, V.
AU - Vijaykrishnan, N.
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.
AB - This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.
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U2 - 10.1109/ICVD.2005.79
DO - 10.1109/ICVD.2005.79
M3 - Conference contribution
AN - SCOPUS:27944464913
SN - 0769522645
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 736
EP - 741
BT - Proceedings of the 18th International Conference on VLSI Design
T2 - 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Y2 - 3 January 2005 through 7 January 2005
ER -