Device circuit co-design using classical and non-classical III-V multi-gate quantum-well FETs (MuQFETs)

Lu Liu; Vinay Saripalli; Vijaykrishnan Narayanan; Suman Datta

doi:10.1109/IEDM.2011.6131489

Device circuit co-design using classical and non-classical III-V multi-gate quantum-well FETs (MuQFETs)

Lu Liu, Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents ultra low-power reconfigurable logic and single-electron memory architecture to enable sub-300 mV V _CC operation using classical and non-classical (NC) III-V Multi-Gate Quantum Well Field Effect Transistors (MuQFETs). A strained In _0.7Ga _0.3As quantum-well based classical multi-gate FET and an In _0.7Ga _0.3As MuQFET operating in Coulomb-blockade mode with tunable tunnel barrier are experimentally demonstrated. Reconfigurable Binary Decision Diagram (BDD) logic and single-electron SRAM implementations based on III-V MuQFETs are demonstrated. Using device models well calibrated to experiments, we show 50% reduction in minimum-energy for logic, and 75x reduction in dynamic power for memory at equivalent performance over Si CMOS logic.

Original language	English (US)
Title of host publication	2011 International Electron Devices Meeting, IEDM 2011
DOIs	https://doi.org/10.1109/IEDM.2011.6131489
State	Published - Dec 1 2011
Event	2011 IEEE International Electron Devices Meeting, IEDM 2011 - Washington, DC, United States Duration: Dec 5 2011 → Dec 7 2011

Other

Other	2011 IEEE International Electron Devices Meeting, IEDM 2011
Country	United States
City	Washington, DC
Period	12/5/11 → 12/7/11

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2011.6131489

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title = "Device circuit co-design using classical and non-classical III-V multi-gate quantum-well FETs (MuQFETs)",

abstract = "This paper presents ultra low-power reconfigurable logic and single-electron memory architecture to enable sub-300 mV V CC operation using classical and non-classical (NC) III-V Multi-Gate Quantum Well Field Effect Transistors (MuQFETs). A strained In 0.7Ga 0.3As quantum-well based classical multi-gate FET and an In 0.7Ga 0.3As MuQFET operating in Coulomb-blockade mode with tunable tunnel barrier are experimentally demonstrated. Reconfigurable Binary Decision Diagram (BDD) logic and single-electron SRAM implementations based on III-V MuQFETs are demonstrated. Using device models well calibrated to experiments, we show 50% reduction in minimum-energy for logic, and 75x reduction in dynamic power for memory at equivalent performance over Si CMOS logic.",

author = "Lu Liu and Vinay Saripalli and Vijaykrishnan Narayanan and Suman Datta",

year = "2011",

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doi = "10.1109/IEDM.2011.6131489",

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AU - Datta, Suman

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N2 - This paper presents ultra low-power reconfigurable logic and single-electron memory architecture to enable sub-300 mV V CC operation using classical and non-classical (NC) III-V Multi-Gate Quantum Well Field Effect Transistors (MuQFETs). A strained In 0.7Ga 0.3As quantum-well based classical multi-gate FET and an In 0.7Ga 0.3As MuQFET operating in Coulomb-blockade mode with tunable tunnel barrier are experimentally demonstrated. Reconfigurable Binary Decision Diagram (BDD) logic and single-electron SRAM implementations based on III-V MuQFETs are demonstrated. Using device models well calibrated to experiments, we show 50% reduction in minimum-energy for logic, and 75x reduction in dynamic power for memory at equivalent performance over Si CMOS logic.

AB - This paper presents ultra low-power reconfigurable logic and single-electron memory architecture to enable sub-300 mV V CC operation using classical and non-classical (NC) III-V Multi-Gate Quantum Well Field Effect Transistors (MuQFETs). A strained In 0.7Ga 0.3As quantum-well based classical multi-gate FET and an In 0.7Ga 0.3As MuQFET operating in Coulomb-blockade mode with tunable tunnel barrier are experimentally demonstrated. Reconfigurable Binary Decision Diagram (BDD) logic and single-electron SRAM implementations based on III-V MuQFETs are demonstrated. Using device models well calibrated to experiments, we show 50% reduction in minimum-energy for logic, and 75x reduction in dynamic power for memory at equivalent performance over Si CMOS logic.

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