DFLAP: A dynamic frequency linear array processor

N. Vijaykrishnan, N. Ranganathan, Naveen Bhavanishankar

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

In this paper, a novel dynamic frequency based SIMD linear array processor (DFLAP) for image processing applications is proposed. The operating clock frequency of the processor is varied dynamically between 400 MHz and 50 MHz based on the operation performed in order to enhance the processor throughput. An efficient implementation for the dynamic clocking unit (DCU) which enables dynamic switching of clock frequencies is presented. Each processing element in the linear array contains an 8-bit arithmetic/logic unit, an 8×8 single-cycle multiplier, a shifter, a bidirectional neighbor communication unit, a 32×8 dual port SRAM, and a DCU. The architecture was designed and implemented using CADENCE design tools. Several low-level image processing tasks have been mapped onto the architecture to demonstrate the effectiveness of the dynamic frequency based architecture.

Original languageEnglish (US)
Pages1007-1010
Number of pages4
Publication statusPublished - Dec 1 1996
EventProceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3) - Lausanne, Switz
Duration: Sep 16 1996Sep 19 1996

Other

OtherProceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3)
CityLausanne, Switz
Period9/16/969/19/96

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering

Cite this

Vijaykrishnan, N., Ranganathan, N., & Bhavanishankar, N. (1996). DFLAP: A dynamic frequency linear array processor. 1007-1010. Paper presented at Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3), Lausanne, Switz, .