Abstract
Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches have been proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, seldom mapping algorithms that consider the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Thus, this paper presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000-ppm defects.
| Original language | English (US) |
|---|---|
| Article number | 7373670 |
| Pages (from-to) | 2321-2334 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 24 |
| Issue number | 6 |
| DOIs | |
| State | Published - Jun 1 2016 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. / Huang, Ching Yi; Li, Yun Jui; Liu, Chian Wei; Wang, Chun Yao; Chen, Yung Chih; Datta, Suman; Narayanan, Vijaykrishnan.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 6, 7373670, 01.06.2016, p. 2321-2334.Research output: Contribution to journal › Article
TY - JOUR
T1 - Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays
AU - Huang, Ching Yi
AU - Li, Yun Jui
AU - Liu, Chian Wei
AU - Wang, Chun Yao
AU - Chen, Yung Chih
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
PY - 2016/6/1
Y1 - 2016/6/1
N2 - Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches have been proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, seldom mapping algorithms that consider the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Thus, this paper presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000-ppm defects.
AB - Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches have been proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, seldom mapping algorithms that consider the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Thus, this paper presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000-ppm defects.
UR - http://www.scopus.com/inward/record.url?scp=84953315301&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84953315301&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2015.2506780
DO - 10.1109/TVLSI.2015.2506780
M3 - Article
AN - SCOPUS:84953315301
VL - 24
SP - 2321
EP - 2334
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 6
M1 - 7373670
ER -