Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays

Ching Yi Huang, Yun Jui Li, Chian Wei Liu, Chun Yao Wang, Yung Chih Chen, Suman Datta, Vijaykrishnan Narayanan

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches have been proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, seldom mapping algorithms that consider the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Thus, this paper presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000-ppm defects.

Original languageEnglish (US)
Article number7373670
Pages (from-to)2321-2334
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number6
DOIs
StatePublished - Jun 1 2016

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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