Drain-offset ZnO thin film transistors for high voltage operations

Yiyang Gong, Thomas N. Jackson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We report ZnO thin film transistors (TFTs) with offset drain for high voltage operation. Offset-drain FETs using Si, a-Si:H, and pentacene have been previously demonstrated [1,2,3]. The TFTs use a bottom gate structure with Al2O3 gate dielectric and ZnO active layers deposited by plasma enhanced atomic layer deposition (PEALD). As the drain offset is increased from 0 μm to 2 μm· the drain-to-source breakdown voltage increased from 33 V to 82 V, while the linear mobility decreased from 10 cm2/Vs to 4 cm2/Vs. Our process flow is simple and compatible with glass and polymeric substrates.

Original languageEnglish (US)
Title of host publication74th Annual Device Research Conference, DRC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509028276
DOIs
StatePublished - Aug 22 2016
Event74th Annual Device Research Conference, DRC 2016 - Newark, United States
Duration: Jun 19 2016Jun 22 2016

Publication series

NameDevice Research Conference - Conference Digest, DRC
Volume2016-August
ISSN (Print)1548-3770

Other

Other74th Annual Device Research Conference, DRC 2016
CountryUnited States
CityNewark
Period6/19/166/22/16

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Gong, Y., & Jackson, T. N. (2016). Drain-offset ZnO thin film transistors for high voltage operations. In 74th Annual Device Research Conference, DRC 2016 [7548469] (Device Research Conference - Conference Digest, DRC; Vol. 2016-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC.2016.7548469