Droop mitigating last level cache architecture for STTRAM

Radha Krishna Aluru, Swaroop Ghosh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)

    Abstract

    Spin-Transfer Torque Random Access Memory (STTRAM) is one of the emerging Non-Volatile Memory (NVM) technologies especially preferred for the Last Level Cache (LLC). The amount of current needed to switch the magnetization is high (∼100ßA per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop, the write operation fails especially, when the farthest bank of the cache is accessed. In this paper, we propose a new cache architecture to mitigate this problem of droop and make the write operation successful. Instead of continuously writing the entire cache line (512-bit) in a single bank, the proposed architecture writes 64-bits in multiple physically separated locations across the cache. The simulation results obtained (both circuit and micro-architectural) comparing our proposed architecture against the conventional are found to be 1.96% (IPC) and 5.21% (energy).

    Original languageEnglish (US)
    Title of host publicationProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages262-265
    Number of pages4
    ISBN (Electronic)9783981537093
    DOIs
    StatePublished - May 11 2017
    Event20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland
    Duration: Mar 27 2017Mar 31 2017

    Publication series

    NameProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017

    Other

    Other20th Design, Automation and Test in Europe, DATE 2017
    CountrySwitzerland
    CitySwisstech, Lausanne
    Period3/27/173/31/17

    Fingerprint

    Torque
    Data storage equipment
    Magnetization
    Switches
    Networks (circuits)
    Electric potential

    All Science Journal Classification (ASJC) codes

    • Computer Networks and Communications
    • Hardware and Architecture
    • Safety, Risk, Reliability and Quality

    Cite this

    Aluru, R. K., & Ghosh, S. (2017). Droop mitigating last level cache architecture for STTRAM. In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017 (pp. 262-265). [7926994] (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2017.7926994
    Aluru, Radha Krishna ; Ghosh, Swaroop. / Droop mitigating last level cache architecture for STTRAM. Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 262-265 (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).
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    title = "Droop mitigating last level cache architecture for STTRAM",
    abstract = "Spin-Transfer Torque Random Access Memory (STTRAM) is one of the emerging Non-Volatile Memory (NVM) technologies especially preferred for the Last Level Cache (LLC). The amount of current needed to switch the magnetization is high (∼100{\ss}A per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop, the write operation fails especially, when the farthest bank of the cache is accessed. In this paper, we propose a new cache architecture to mitigate this problem of droop and make the write operation successful. Instead of continuously writing the entire cache line (512-bit) in a single bank, the proposed architecture writes 64-bits in multiple physically separated locations across the cache. The simulation results obtained (both circuit and micro-architectural) comparing our proposed architecture against the conventional are found to be 1.96{\%} (IPC) and 5.21{\%} (energy).",
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    Aluru, RK & Ghosh, S 2017, Droop mitigating last level cache architecture for STTRAM. in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017., 7926994, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers Inc., pp. 262-265, 20th Design, Automation and Test in Europe, DATE 2017, Swisstech, Lausanne, Switzerland, 3/27/17. https://doi.org/10.23919/DATE.2017.7926994

    Droop mitigating last level cache architecture for STTRAM. / Aluru, Radha Krishna; Ghosh, Swaroop.

    Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 262-265 7926994 (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    Aluru RK, Ghosh S. Droop mitigating last level cache architecture for STTRAM. In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 262-265. 7926994. (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017). https://doi.org/10.23919/DATE.2017.7926994