Droop mitigating last level cache architecture for STTRAM

Radha Krishna Aluru, Swaroop Ghosh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (SciVal)

    Abstract

    Spin-Transfer Torque Random Access Memory (STTRAM) is one of the emerging Non-Volatile Memory (NVM) technologies especially preferred for the Last Level Cache (LLC). The amount of current needed to switch the magnetization is high (∼100ßA per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop, the write operation fails especially, when the farthest bank of the cache is accessed. In this paper, we propose a new cache architecture to mitigate this problem of droop and make the write operation successful. Instead of continuously writing the entire cache line (512-bit) in a single bank, the proposed architecture writes 64-bits in multiple physically separated locations across the cache. The simulation results obtained (both circuit and micro-architectural) comparing our proposed architecture against the conventional are found to be 1.96% (IPC) and 5.21% (energy).

    Original languageEnglish (US)
    Title of host publicationProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages262-265
    Number of pages4
    ISBN (Electronic)9783981537093
    DOIs
    StatePublished - May 11 2017
    Event20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland
    Duration: Mar 27 2017Mar 31 2017

    Publication series

    NameProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017

    Other

    Other20th Design, Automation and Test in Europe, DATE 2017
    Country/TerritorySwitzerland
    CitySwisstech, Lausanne
    Period3/27/173/31/17

    All Science Journal Classification (ASJC) codes

    • Computer Networks and Communications
    • Hardware and Architecture
    • Safety, Risk, Reliability and Quality

    Fingerprint

    Dive into the research topics of 'Droop mitigating last level cache architecture for STTRAM'. Together they form a unique fingerprint.

    Cite this