We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport  and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2-4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.