Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations

Niladri N. Mojumder, Sumeet Kumar Gupta, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2-4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.

Original languageEnglish (US)
Title of host publication69th Device Research Conference, DRC 2011 - Conference Digest
Pages67-68
Number of pages2
DOIs
StatePublished - Dec 1 2011
Event69th Device Research Conference, DRC 2011 - Santa Barbara, CA, United States
Duration: Jun 20 2011Jun 22 2011

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Other

Other69th Device Research Conference, DRC 2011
CountryUnited States
CitySanta Barbara, CA
Period6/20/116/22/11

Fingerprint

Magnetic anisotropy
Tunnelling magnetoresistance
Torque
Transistors
Memory architecture
Tunnel junctions
Electric currents
Macros
Tunnels
Current density
Networks (circuits)
Electric potential
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Mojumder, N. N., Gupta, S. K., & Roy, K. (2011). Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations. In 69th Device Research Conference, DRC 2011 - Conference Digest (pp. 67-68). [5994466] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2011.5994466
Mojumder, Niladri N. ; Gupta, Sumeet Kumar ; Roy, Kaushik. / Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations. 69th Device Research Conference, DRC 2011 - Conference Digest. 2011. pp. 67-68 (Device Research Conference - Conference Digest, DRC).
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abstract = "We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70{\%} lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2-4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.",
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Mojumder, NN, Gupta, SK & Roy, K 2011, Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations. in 69th Device Research Conference, DRC 2011 - Conference Digest., 5994466, Device Research Conference - Conference Digest, DRC, pp. 67-68, 69th Device Research Conference, DRC 2011, Santa Barbara, CA, United States, 6/20/11. https://doi.org/10.1109/DRC.2011.5994466

Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations. / Mojumder, Niladri N.; Gupta, Sumeet Kumar; Roy, Kaushik.

69th Device Research Conference, DRC 2011 - Conference Digest. 2011. p. 67-68 5994466 (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2-4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.

AB - We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2-4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.

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BT - 69th Device Research Conference, DRC 2011 - Conference Digest

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Mojumder NN, Gupta SK, Roy K. Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations. In 69th Device Research Conference, DRC 2011 - Conference Digest. 2011. p. 67-68. 5994466. (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2011.5994466