Dual pillar spin-transfer torque MRAMs for low power applications

Niladri N. Mojumder, Xuanyao Fong, Charles Augustine, Sumeet K. Gupta, Sri Harsha Choday, Kaushik Roy

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

Electron-spin based data storage for on-chip memories has the potential for ultra-high density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we discuss the design challenges associated with spin-transfer torque (STT) MRAM in its state-of-the-art configuration. We propose an alternative bit cell configuration and three new genres of magnetic tunnel junction (MTJ) structures to improve STT-MRAM bit cell stabilities, write endurance, and reduce write energy consumption. The proposed multi-port, multi-pillar MTJ structures offer the unique possibility of electrical and spatial isolation of memory read and write. In order to realize ultralow power under process variations, we propose device, bit-cell and architecture level design techniques. Such design alternatives at multiple levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

Original languageEnglish (US)
Article number14
JournalACM Journal on Emerging Technologies in Computing Systems
Volume9
Issue number2
DOIs
StatePublished - Oct 21 2013

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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