Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays

Yun Jui Li, Ching Yi Huang, Chia Cheng Wu, Yung Chih Chen, Chun Yao Wang, Suman Datta, Vijaykrishnan Narayanan

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks.

Original languageEnglish (US)
Article number7811262
Pages (from-to)1477-1489
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number4
DOIs
StatePublished - Apr 1 2017

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Single electron transistors
Program processors
Defects
Boolean functions
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Li, Yun Jui ; Huang, Ching Yi ; Wu, Chia Cheng ; Chen, Yung Chih ; Wang, Chun Yao ; Datta, Suman ; Narayanan, Vijaykrishnan. / Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 ; Vol. 25, No. 4. pp. 1477-1489.
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Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. / Li, Yun Jui; Huang, Ching Yi; Wu, Chia Cheng; Chen, Yung Chih; Wang, Chun Yao; Datta, Suman; Narayanan, Vijaykrishnan.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 4, 7811262, 01.04.2017, p. 1477-1489.

Research output: Contribution to journalArticle

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