TY - JOUR
T1 - Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays
AU - Li, Yun Jui
AU - Huang, Ching Yi
AU - Wu, Chia Cheng
AU - Chen, Yung Chih
AU - Wang, Chun Yao
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/4
Y1 - 2017/4
N2 - Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks.
AB - Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks.
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U2 - 10.1109/TVLSI.2016.2639533
DO - 10.1109/TVLSI.2016.2639533
M3 - Article
AN - SCOPUS:85009858706
SN - 1063-8210
VL - 25
SP - 1477
EP - 1489
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 4
M1 - 7811262
ER -