Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors

Amar Rasheed, M. Cotter, B. Smith, D. Levan, S. Phoha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a dynamically run-time reconfigurable power aware cryptographic processor for secure autonomous encryption. The design proposes the implementation of a dynamically reconfigurable AES cryptography process on an FPGA. The proposed design encompasses a microarchitecture which is variously power, latency, and throughput optimized via hardware acceleration and partial reconfiguration by a multi-level autonomic controller and a data router to enable tradeoffs under changing operational requirements within resource constraints. The multi-level controller decides on the appropriate configuration based on varying operational workloads to characterize the effect that time-varying task parameters have on the hardware architecture, to enable a run-time tradeoff of performance and resources usage (Key length, computational efficiency, latency and throughput).

Original languageEnglish (US)
Title of host publication2016 IEEE 35th International Performance Computing and Communications Conference, IPCCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509052523
DOIs
StatePublished - Jan 17 2017
Event35th IEEE International Performance Computing and Communications Conference, IPCCC 2016 - Las Vegas, United States
Duration: Dec 9 2016Dec 11 2016

Publication series

Name2016 IEEE 35th International Performance Computing and Communications Conference, IPCCC 2016

Other

Other35th IEEE International Performance Computing and Communications Conference, IPCCC 2016
CountryUnited States
CityLas Vegas
Period12/9/1612/11/16

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture

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  • Cite this

    Rasheed, A., Cotter, M., Smith, B., Levan, D., & Phoha, S. (2017). Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors. In 2016 IEEE 35th International Performance Computing and Communications Conference, IPCCC 2016 [7820667] (2016 IEEE 35th International Performance Computing and Communications Conference, IPCCC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PCCC.2016.7820667