EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors

Hsiang Yun Cheng, Matt Poremba, Marges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut Kandemir, Jack Sampson, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Power management for large last-level caches (LLCs) is important in chip-multiprocessors (CMPs), as the leakage power of LLCs accounts for a significant fraction of the limited on-chip power budget. Since not all workloads need the entire cache, portions of a shared LLC can be disabled to save energy. In this paper, we explore different design choices, from circuit-level cache organization to micro-architectural management policies, to propose a lowoverhead run-time mechanism for energy reduction in the shared LLC. Results show that our design (EECache) provides 14.1% energy saving at only 1.2% performance degradation on average, with negligible hardware overhead.

Original languageEnglish (US)
Title of host publicationISLPED 2014 - Proceedings of the 2014 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages303-306
Number of pages4
ISBN (Print)9781450329750
DOIs
StatePublished - 2014
Event2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014 - San Diego, CA, United States
Duration: Aug 11 2014Aug 13 2014

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2014 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2014
Country/TerritoryUnited States
CitySan Diego, CA
Period8/11/148/13/14

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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