Effect of power optimizations on soft error rate

Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Y. Xie, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingChapter

8 Scopus citations

Abstract

Due to technology scaling, devices are getting smaller, faster and operating at lower voltages. The reduced nodal capacitances and supply voltages coupled with more dense and larger chips are increasing soft errors and making them an important design constraint. As designers aggressively address the excessive power consumption problem that is considered as a major design limiter they need to be aware of the impact of the power optimizations on the soft error rates(SER). In this chapter, we analyze the effect of increasing threshold voltage and reducing the operating voltages, widely used for reducing power consumption, on the soft error rate. While reducing the operating voltage increases the susceptibility to soft errors, increasing the threshold voltages offers mixed results. We find that increasing threshold voltage (Vt) improves SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses. We also show that, in certain circuits, clever use of high Vt can improve the robustness to soft errors.

Original languageEnglish (US)
Title of host publicationVLSI-SOC
Subtitle of host publicationFrom Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003)
EditorsManfred Glesner Leandro, Indrusiak, Hans Eveking, Ricardo Reis, Vincent Mooney
Pages1-20
Number of pages20
DOIs
StatePublished - Oct 4 2006

Publication series

NameIFIP International Federation for Information Processing
Volume200
ISSN (Print)1571-5736

All Science Journal Classification (ASJC) codes

  • Information Systems and Management

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    Degalahal, V., Ramanarayanan, R., Vijaykrishnan, N., Xie, Y., & Irwin, M. J. (2006). Effect of power optimizations on soft error rate. In M. G. Leandro, Indrusiak, H. Eveking, R. Reis, & V. Mooney (Eds.), VLSI-SOC: From Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) (pp. 1-20). (IFIP International Federation for Information Processing; Vol. 200). https://doi.org/10.1007/0-387-33403-3_1