Efficient complex operators for irregular codes

Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Scopus citations

Abstract

Complex "fat operators" are important contributors to the efficiency of specialized hardware. This paper introduces two new techniques for constructing efficient fat operators featuring up to dozens of operations with arbitrary and irregular data and memory dependencies. These techniques focus on minimizing critical path length and load-use delay, which are key concerns for irregular computations. Selective Depipelining(SDP) is a pipelining technique that allows fat operators containing several, possibly dependent, memory operations. SDP allows memory requests to operate at a faster clock rate than the datapath, saving power in the datapath and improving memory performance. Cachelets are small, customized, distributed L0 caches embedded in the datapath to reduce load-use latency. We apply these techniques to Conservation Cores(c-cores) to produce coprocessors that accelerate irregular code regions while still providing superior energy efficiency. On average, these enhanced c-cores reduce EDP by 2x and area by 35% relative to c-cores. They are up to 2.5x faster than a general-purpose processor and reduce energy consumption by up to 8x for a variety of irregular applications including several SPECINT benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Pages491-502
Number of pages12
DOIs
StatePublished - May 17 2011
Event17th International Symposium on High-Performance Computer Architecture, HPCA 2011 - San Antonio, TX, United States
Duration: Feb 12 2011Feb 16 2011

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Country/TerritoryUnited States
CitySan Antonio, TX
Period2/12/112/16/11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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