Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications

Vishal Deep, Tarek A. Elarabi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The increasing industrial demand for low data-rate and low power networking protocols for IoT communications from past several years led to the development of ZigBee technology. As a result of advancement in VLSI technologies, development of more power efficient, accurate, and small digital ZigBee transmitter design has become achievable but yet challenging. This paper presents digital design and FPGA PoC implementation for the 2.4 GHz-band digital ZigBee transmitter. The proposed hardware design of the transmitter described by utilizing Verilog Hardware Description Language and the prototype implementation is done by employing Xilinx Vivado 2016.2. The paper demonstrates the design of the four building blocks of an energy efficient digital ZigBee transmitter; i.e. cyclic redundancy check, bit-to-symbol block, symbol-to-chip block, and offset quadrature phase shift keying Modulator. Simulation waveform verifies functionality of the transmitter and its low power and low data-rate suitability for Internet of Things' applications.

Original languageEnglish (US)
Title of host publicationProceedings - International Conference on Signals and Systems, ICSigSys 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages261-265
Number of pages5
ISBN (Electronic)9781509067480
DOIs
StatePublished - Jun 30 2017
Event1st IEEE International Conference on Signals and Systems, ICSigSys 2017 - Bali, Indonesia
Duration: May 16 2017May 18 2017

Publication series

NameProceedings - International Conference on Signals and Systems, ICSigSys 2017

Other

Other1st IEEE International Conference on Signals and Systems, ICSigSys 2017
CountryIndonesia
CityBali
Period5/16/175/18/17

Fingerprint

Zigbee
transmitters
Transmitters
hardware
Hardware
Computer hardware description languages
hardware description languages
quadrature phase shift keying
Quadrature phase shift keying
very large scale integration
redundancy
Modulators
Redundancy
Field programmable gate arrays (FPGA)
modulators
waveforms
communication
chips
prototypes
Internet of things

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition
  • Signal Processing

Cite this

Deep, V., & Elarabi, T. A. (2017). Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications. In Proceedings - International Conference on Signals and Systems, ICSigSys 2017 (pp. 261-265). [7967053] (Proceedings - International Conference on Signals and Systems, ICSigSys 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSIGSYS.2017.7967053
Deep, Vishal ; Elarabi, Tarek A. / Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications. Proceedings - International Conference on Signals and Systems, ICSigSys 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 261-265 (Proceedings - International Conference on Signals and Systems, ICSigSys 2017).
@inproceedings{470926a3f0e34a1db39760577476c841,
title = "Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications",
abstract = "The increasing industrial demand for low data-rate and low power networking protocols for IoT communications from past several years led to the development of ZigBee technology. As a result of advancement in VLSI technologies, development of more power efficient, accurate, and small digital ZigBee transmitter design has become achievable but yet challenging. This paper presents digital design and FPGA PoC implementation for the 2.4 GHz-band digital ZigBee transmitter. The proposed hardware design of the transmitter described by utilizing Verilog Hardware Description Language and the prototype implementation is done by employing Xilinx Vivado 2016.2. The paper demonstrates the design of the four building blocks of an energy efficient digital ZigBee transmitter; i.e. cyclic redundancy check, bit-to-symbol block, symbol-to-chip block, and offset quadrature phase shift keying Modulator. Simulation waveform verifies functionality of the transmitter and its low power and low data-rate suitability for Internet of Things' applications.",
author = "Vishal Deep and Elarabi, {Tarek A.}",
year = "2017",
month = "6",
day = "30",
doi = "10.1109/ICSIGSYS.2017.7967053",
language = "English (US)",
series = "Proceedings - International Conference on Signals and Systems, ICSigSys 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "261--265",
booktitle = "Proceedings - International Conference on Signals and Systems, ICSigSys 2017",
address = "United States",

}

Deep, V & Elarabi, TA 2017, Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications. in Proceedings - International Conference on Signals and Systems, ICSigSys 2017., 7967053, Proceedings - International Conference on Signals and Systems, ICSigSys 2017, Institute of Electrical and Electronics Engineers Inc., pp. 261-265, 1st IEEE International Conference on Signals and Systems, ICSigSys 2017, Bali, Indonesia, 5/16/17. https://doi.org/10.1109/ICSIGSYS.2017.7967053

Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications. / Deep, Vishal; Elarabi, Tarek A.

Proceedings - International Conference on Signals and Systems, ICSigSys 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 261-265 7967053 (Proceedings - International Conference on Signals and Systems, ICSigSys 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications

AU - Deep, Vishal

AU - Elarabi, Tarek A.

PY - 2017/6/30

Y1 - 2017/6/30

N2 - The increasing industrial demand for low data-rate and low power networking protocols for IoT communications from past several years led to the development of ZigBee technology. As a result of advancement in VLSI technologies, development of more power efficient, accurate, and small digital ZigBee transmitter design has become achievable but yet challenging. This paper presents digital design and FPGA PoC implementation for the 2.4 GHz-band digital ZigBee transmitter. The proposed hardware design of the transmitter described by utilizing Verilog Hardware Description Language and the prototype implementation is done by employing Xilinx Vivado 2016.2. The paper demonstrates the design of the four building blocks of an energy efficient digital ZigBee transmitter; i.e. cyclic redundancy check, bit-to-symbol block, symbol-to-chip block, and offset quadrature phase shift keying Modulator. Simulation waveform verifies functionality of the transmitter and its low power and low data-rate suitability for Internet of Things' applications.

AB - The increasing industrial demand for low data-rate and low power networking protocols for IoT communications from past several years led to the development of ZigBee technology. As a result of advancement in VLSI technologies, development of more power efficient, accurate, and small digital ZigBee transmitter design has become achievable but yet challenging. This paper presents digital design and FPGA PoC implementation for the 2.4 GHz-band digital ZigBee transmitter. The proposed hardware design of the transmitter described by utilizing Verilog Hardware Description Language and the prototype implementation is done by employing Xilinx Vivado 2016.2. The paper demonstrates the design of the four building blocks of an energy efficient digital ZigBee transmitter; i.e. cyclic redundancy check, bit-to-symbol block, symbol-to-chip block, and offset quadrature phase shift keying Modulator. Simulation waveform verifies functionality of the transmitter and its low power and low data-rate suitability for Internet of Things' applications.

UR - http://www.scopus.com/inward/record.url?scp=85026626552&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85026626552&partnerID=8YFLogxK

U2 - 10.1109/ICSIGSYS.2017.7967053

DO - 10.1109/ICSIGSYS.2017.7967053

M3 - Conference contribution

T3 - Proceedings - International Conference on Signals and Systems, ICSigSys 2017

SP - 261

EP - 265

BT - Proceedings - International Conference on Signals and Systems, ICSigSys 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Deep V, Elarabi TA. Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications. In Proceedings - International Conference on Signals and Systems, ICSigSys 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 261-265. 7967053. (Proceedings - International Conference on Signals and Systems, ICSigSys 2017). https://doi.org/10.1109/ICSIGSYS.2017.7967053