Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration

E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, Vijaykrishnan Narayanan

Research output: Contribution to conferencePaper

Abstract

This paper proposes a new CLB architecture for FPGAs and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10% of the switch matrices to be reconfigured to correct the errors.

Original languageEnglish (US)
Number of pages1
StatePublished - Jun 20 2005
EventACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States
Duration: Feb 20 2005Feb 22 2005

Other

OtherACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
CountryUnited States
CityMonterey, CA
Period2/20/052/22/05

Fingerprint

Field programmable gate arrays (FPGA)
Error detection
Switches
Shift registers
Networks (circuits)
Testing
Error correction

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Reddy, E. S. S., Chandrasekhar, V., Sashikanth, M., Kamakoti, V., & Narayanan, V. (2005). Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.
Reddy, E. Syam Sundar ; Chandrasekhar, Vikram ; Sashikanth, M. ; Kamakoti, V. ; Narayanan, Vijaykrishnan. / Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.1 p.
@conference{82f11c9cb9ca439e8518ed10312adc05,
title = "Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration",
abstract = "This paper proposes a new CLB architecture for FPGAs and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10{\%} of the switch matrices to be reconfigured to correct the errors.",
author = "Reddy, {E. Syam Sundar} and Vikram Chandrasekhar and M. Sashikanth and V. Kamakoti and Vijaykrishnan Narayanan",
year = "2005",
month = "6",
day = "20",
language = "English (US)",
note = "ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 ; Conference date: 20-02-2005 Through 22-02-2005",

}

Reddy, ESS, Chandrasekhar, V, Sashikanth, M, Kamakoti, V & Narayanan, V 2005, 'Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration' Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States, 2/20/05 - 2/22/05, .

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration. / Reddy, E. Syam Sundar; Chandrasekhar, Vikram; Sashikanth, M.; Kamakoti, V.; Narayanan, Vijaykrishnan.

2005. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.

Research output: Contribution to conferencePaper

TY - CONF

T1 - Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration

AU - Reddy, E. Syam Sundar

AU - Chandrasekhar, Vikram

AU - Sashikanth, M.

AU - Kamakoti, V.

AU - Narayanan, Vijaykrishnan

PY - 2005/6/20

Y1 - 2005/6/20

N2 - This paper proposes a new CLB architecture for FPGAs and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10% of the switch matrices to be reconfigured to correct the errors.

AB - This paper proposes a new CLB architecture for FPGAs and associated testing and reconfiguration techniques that detect single routing/interconnect errors and correct them using partial reconfiguration. The results of error detection are propagated to a single output port by a chain-like shift register, which are used to reduce the segment of the routing architecture that has to be reconfigured. The error is corrected by partially reconfiguring the above minimal segment alone, thereby reducing the time for reconfiguration. The proposed testing technique detects all possible routing errors that affects the logic of the circuit, including bridging faults. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA. Empirically, our technique detected all single interconnect errors in benchmark circuits. In addition, for the majority of errors, our correction technique required less than 10% of the switch matrices to be reconfigured to correct the errors.

UR - http://www.scopus.com/inward/record.url?scp=20344403541&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20344403541&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:20344403541

ER -

Reddy ESS, Chandrasekhar V, Sashikanth M, Kamakoti V, Narayanan V. Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration. 2005. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.