Electrical properties of p- and n-type silicon nanowires

Yanfeng Wang, Marco Cabassi, Tsung Ta Ho, Kok Keong Lew, Joan Marie Redwing, Theresa Mayer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type and n-type silicon nanowires (SiNWs), are presented. The SiNWs used in the studies are synthesized by template-directed vapor-liquid-solid (VLS) growth using 10% SiH 4 in H 2 as silicon gas source. The data show a clear trend to lower resistivity when b- and p-dopants are unintentionally added during VLS growth. The results of the study show that future efforts should address the source of the high p-type background doping concentration in VLS grown SiNWs to facilitate improvements in the properties of n-channel devices.

Original languageEnglish (US)
Title of host publicationDevice Research Conference - Conference Digest, 62nd DRC
Pages23-24
Number of pages2
DOIs
Publication statusPublished - Dec 1 2004
EventDevice Research Conference - Conference Digest, 62nd DRC - Notre Dame, IN, United States
Duration: Jun 21 2004Jun 23 2004

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Other

OtherDevice Research Conference - Conference Digest, 62nd DRC
CountryUnited States
CityNotre Dame, IN
Period6/21/046/23/04

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Wang, Y., Cabassi, M., Ho, T. T., Lew, K. K., Redwing, J. M., & Mayer, T. (2004). Electrical properties of p- and n-type silicon nanowires. In Device Research Conference - Conference Digest, 62nd DRC (pp. 23-24). [II.A.-6] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2004.1367764