Enabling 3-D design

Pilot-level fabrication of wafers integrated into 3-D structures have been processed. These demonstrate the repeatability and reliability of the Au/Sn penetration/post-joining process and a fine-pitch TSV process suitable for thin wafer handling. Reliability testing shows that this 3-D architecture exceeds customer requirements. An IC design with stacked memory demonstrated a 1000-fold increase in speed with a 100-fold decrease in power consumption. This shows the groundbreaking capability of using 3-D processing to combine the design capabilities of a fabless company with the processing capabilities of both front-end and packaging foundries to create a high-performance device without resorting to leading-edge transistor geometries.