Enabling power-efficient designs with III-V tunnel FETs

Moon Seok Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

Original languageEnglish (US)
Title of host publicationTechnical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479936229
DOIs
StatePublished - Dec 5 2014
Event36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014 - San Diego, United States
Duration: Oct 19 2014Oct 22 2014

Publication series

NameTechnical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
ISSN (Print)1550-8781

Other

Other36th IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2014
CountryUnited States
CitySan Diego
Period10/19/1410/22/14

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Kim, M. S., Liu, H., Swaminathan, K., Li, X., Datta, S., & Narayanan, V. (2014). Enabling power-efficient designs with III-V tunnel FETs. In Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC [6978551] (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSICS.2014.6978551