Energy and timing characterization of VLSI charge-pump phase-locked loops

D. Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5% of circuit level simulation numbers.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
EditorsDong S. Ha, Richard Auletta, John Chickanosky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages341-344
Number of pages4
ISBN (Electronic)0780381823, 9780780381827
DOIs
StatePublished - Jan 1 2003
EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
Duration: Sep 17 2003Sep 20 2003

Other

OtherIEEE International SOC Conference, SOCC 2003
CountryUnited States
CityPortland
Period9/17/039/20/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Duarte, D., Narayanan, V., & Irwin, M. J. (2003). Energy and timing characterization of VLSI charge-pump phase-locked loops. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 341-344). [1241539] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241539