Energy centric model of SRAM write operation for improved energy and error rates

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We propose an energy centric model of SRAM write operation. The model provides useful insights about energy and write error rates. We introduce the concept of intrinsic energy margin induced errors. The proposed model is employed for evaluating various write assist mechanisms and their potential in reducing the intrinsic memory error rates. We also demonstrate that this model can be used for optimizing energy of memory arrays.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467361460
DOIs
StatePublished - Nov 7 2013
Event35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
Duration: Sep 22 2013Sep 25 2013

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
CountryUnited States
CitySan Jose, CA
Period9/22/139/25/13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Ghosh, S. (2013). Energy centric model of SRAM write operation for improved energy and error rates. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 [6658429] (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658429