Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages

Vamsi Krishna, N. Ranganathan, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic_freq_sched and Modify_sched. Based on the dynamic frequency scheme, Dynamic_freq_sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify_sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply voltage levels (5.0 V, 3.3 V, 2.4 V), an average energy saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE Comp Soc
Pages440-445
Number of pages6
StatePublished - 1999
EventProceedings of the 1999 12th International Conference on VLSI Design - Goa, India
Duration: Jan 7 1999Jan 10 1999

Other

OtherProceedings of the 1999 12th International Conference on VLSI Design
CityGoa, India
Period1/7/991/10/99

Fingerprint

Electric potential
Networks (circuits)
Scheduling algorithms
Clocks
Energy conservation
Energy utilization
Voltage scaling
High level synthesis

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Krishna, V., Ranganathan, N., & Narayanan, V. (1999). Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages. In Proceedings of the IEEE International Conference on VLSI Design (pp. 440-445). IEEE Comp Soc.
Krishna, Vamsi ; Ranganathan, N. ; Narayanan, Vijaykrishnan. / Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages. Proceedings of the IEEE International Conference on VLSI Design. IEEE Comp Soc, 1999. pp. 440-445
@inproceedings{1f0e885b64874527957b25792acf147a,
title = "Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages",
abstract = "In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic_freq_sched and Modify_sched. Based on the dynamic frequency scheme, Dynamic_freq_sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify_sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply voltage levels (5.0 V, 3.3 V, 2.4 V), an average energy saving of 53.5{\%} (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.",
author = "Vamsi Krishna and N. Ranganathan and Vijaykrishnan Narayanan",
year = "1999",
language = "English (US)",
pages = "440--445",
booktitle = "Proceedings of the IEEE International Conference on VLSI Design",
publisher = "IEEE Comp Soc",

}

Krishna, V, Ranganathan, N & Narayanan, V 1999, Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages. in Proceedings of the IEEE International Conference on VLSI Design. IEEE Comp Soc, pp. 440-445, Proceedings of the 1999 12th International Conference on VLSI Design, Goa, India, 1/7/99.

Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages. / Krishna, Vamsi; Ranganathan, N.; Narayanan, Vijaykrishnan.

Proceedings of the IEEE International Conference on VLSI Design. IEEE Comp Soc, 1999. p. 440-445.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages

AU - Krishna, Vamsi

AU - Ranganathan, N.

AU - Narayanan, Vijaykrishnan

PY - 1999

Y1 - 1999

N2 - In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic_freq_sched and Modify_sched. Based on the dynamic frequency scheme, Dynamic_freq_sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify_sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply voltage levels (5.0 V, 3.3 V, 2.4 V), an average energy saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.

AB - In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic_freq_sched and Modify_sched. Based on the dynamic frequency scheme, Dynamic_freq_sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify_sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply voltage levels (5.0 V, 3.3 V, 2.4 V), an average energy saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=0032759492&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032759492&partnerID=8YFLogxK

M3 - Conference contribution

SP - 440

EP - 445

BT - Proceedings of the IEEE International Conference on VLSI Design

PB - IEEE Comp Soc

ER -

Krishna V, Ranganathan N, Narayanan V. Energy efficient datapath synthesis using Dynamic Frequency Clocking and Multiple Voltages. In Proceedings of the IEEE International Conference on VLSI Design. IEEE Comp Soc. 1999. p. 440-445