Energy-efficient instruction cache using page-based placement

S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Energy consumption is a crucial factor in designing battery- operated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself (called subcache). The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be effective in improving both the energy and energy-delay metrics.

Original languageEnglish (US)
Title of host publicationCASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
PublisherAssociation for Computing Machinery, Inc
Pages229-237
Number of pages9
ISBN (Electronic)1581133995, 9781581133998
DOIs
StatePublished - Nov 16 2001
Event2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001 - Atlanta, United States
Duration: Nov 16 2001Nov 17 2001

Publication series

NameCASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Other

Other2nd International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2001
CountryUnited States
CityAtlanta
Period11/16/0111/17/01

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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