This paper presents possible optimizations to reduce the energy budget for SoC designs that will be used in next generation multimedia systems. Since future multimedia systems will include the processor core(s), the entire memory system, system buses, I/O controllers, system clocking and control and, in wireless applications, RF components, all on one chip, lowering power dissipation in next generation multimedia chips presents a number of design challenges. Possible strategies for managing the power budget in future multimedia SoCs are presented. Reducing the power consumption of the memory system, system control, and system buses are a particular focus.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - Dec 1 1999|
|Event||1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan|
Duration: Oct 20 1999 → Oct 22 1999
All Science Journal Classification (ASJC) codes