Enhancing Address translations in throughput processors via compression

Xulong Tang, Ziyu Zhang, Weizheng Xu, Mahmut Taylan Kandemir, Rami Melhem, Jun Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Efficient memory sharing among multiple compute engines playsan important role in shaping the overall application performanceon CPU-GPU heterogeneous platforms. Unified Virtual Memory(UVM) is a promising feature that allows globally-visible data structures and pointers such that the GPU can access the physical memory space on the CPU side, and take advantage of the host OS pagingmechanism without explicit programmer effort. However, a keyrequirement for the guaranteed performance is effective hardwaresupport of address translation. Particularly, we observe that GPU execution suffers from high TLB miss rates in a UVM environment, especially for irregular and/or memory-intensive applications. In thispaper, we propose simple yet effective compression mechanismsfor address translations to improve GPU TLB hit rates. Specifically,we explore and leverage the TLB compressibility during the execution of GPU applications to design efficient address translationcompression with minimal runtime overhead. Experimental resultsacross 22 applications indicate that our proposed approach significantly improves GPU TLB hit rates, which translate to 12% averageperformance improvement. Particularly, for 16 irregular and/ormemory-intensive applications, the performance improvementsachieved reach up to 69.2%, with an average of 16.3%.

Original languageEnglish (US)
Title of host publicationPACT 2020 - Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages191-204
Number of pages14
ISBN (Electronic)9781450380751
DOIs
StatePublished - Sep 30 2020
Event2020 ACM International Conference on Parallel Architectures and Compilation Techniques, PACT 2020 - Virtual, Online, United States
Duration: Oct 3 2020Oct 7 2020

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Conference

Conference2020 ACM International Conference on Parallel Architectures and Compilation Techniques, PACT 2020
CountryUnited States
CityVirtual, Online
Period10/3/2010/7/20

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Enhancing Address translations in throughput processors via compression'. Together they form a unique fingerprint.

Cite this