Enhancing computation-to-core assignment with physical location information

Orhan Kislal, Jagadish Kotra, Xulong Tang, Mahmut Taylan Kandemir, Myoungsoo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Going beyond a certain number of cores in modern architectures requires an on-chip network more scalable than conventional buses. However, employing an on-chip network in a manycore system (to improve scalability) makes the latencies of the data accesses issued by a core non-uniform. This non-uniformity can play a significant role in shaping the overall application performance. This work presents a novel compiler strategy which involves exposing architecture information to the compiler to enable an optimized computation-to-core mapping. Specifically, we propose a compiler-guided scheme that takes into account the relative positions of (and distances between) cores, last-level caches (LLCs) and memory controllers (MCs) in a manycore system, and generates a mapping of computations to cores with the goal of minimizing the on-chip network traffic. The experimental data collected using a set of 21 multi-threaded applications reveal that, on an average, our approach reduces the on-chip network latency in a 6×6 manycore system by 38.4% in the case of private LLCs, and 43.8% in the case of shared LLCs. These improvements translate to the corresponding execution time improvements of 10.9% and 12.7% for the private LLC and shared LLC based systems, respectively.

Original languageEnglish (US)
Title of host publicationPLDI 2018 - Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation
EditorsJeffrey S. Foster, Dan Grossman, Jeffrey S. Foster
PublisherAssociation for Computing Machinery
Pages312-327
Number of pages16
ISBN (Electronic)9781450356985
DOIs
StatePublished - Jun 11 2018
Event39th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2018 - Philadelphia, United States
Duration: Jun 18 2018Jun 22 2018

Publication series

NameProceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Other

Other39th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2018
CountryUnited States
CityPhiladelphia
Period6/18/186/22/18

All Science Journal Classification (ASJC) codes

  • Software

Fingerprint Dive into the research topics of 'Enhancing computation-to-core assignment with physical location information'. Together they form a unique fingerprint.

  • Cite this

    Kislal, O., Kotra, J., Tang, X., Kandemir, M. T., & Jung, M. (2018). Enhancing computation-to-core assignment with physical location information. In J. S. Foster, D. Grossman, & J. S. Foster (Eds.), PLDI 2018 - Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation (pp. 312-327). (Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)). Association for Computing Machinery. https://doi.org/10.1145/3192366.3192386