Evaluating alternative implementations for LDPC decoder check node function

T. Theocharides, G. Link, E. Swankoski, Vijaykrishnan Narayanan, Mary Jane Irwin, H. Schmit

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Low Density Parity Checks (IDPC) are a method of error detection and correction that are able to achieve near Shannon-limit channel communication. LDPC decoders involve a series of computations between two units, the check node and the bit node. In this paper we propose the use of an approximation unit to perform the check node operation. Additionally, we propose a ROM based look-up table (LUT) as a function approximation technique, to be used with an LDPC decoder. The paper shows that a ROM based LUT achieves better performance than using a piecewise linear approximation method to approximate the LDPC computation function. Furthermore, this paper shows that the ROM LUT method can gradually take over as the selected function approximation technique for computationally intensive demanding VLSI designs as the technology shifts to the nanometer era.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging Trends in VLSI Systems Design
EditorsA. Smailagic, M. Bayoumi
Pages77-82
Number of pages6
DOIs
StatePublished - Sep 24 2004
EventProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States
Duration: Feb 19 2004Feb 20 2004

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

OtherProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
CountryUnited States
CityLafayette, LA
Period2/19/042/20/04

Fingerprint

ROM
Error detection
Error correction

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Theocharides, T., Link, G., Swankoski, E., Narayanan, V., Irwin, M. J., & Schmit, H. (2004). Evaluating alternative implementations for LDPC decoder check node function. In A. Smailagic, & M. Bayoumi (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 77-82). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339511
Theocharides, T. ; Link, G. ; Swankoski, E. ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Schmit, H. / Evaluating alternative implementations for LDPC decoder check node function. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. editor / A. Smailagic ; M. Bayoumi. 2004. pp. 77-82 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).
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Theocharides, T, Link, G, Swankoski, E, Narayanan, V, Irwin, MJ & Schmit, H 2004, Evaluating alternative implementations for LDPC decoder check node function. in A Smailagic & M Bayoumi (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, pp. 77-82, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, Lafayette, LA, United States, 2/19/04. https://doi.org/10.1109/ISVLSI.2004.1339511

Evaluating alternative implementations for LDPC decoder check node function. / Theocharides, T.; Link, G.; Swankoski, E.; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Schmit, H.

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. ed. / A. Smailagic; M. Bayoumi. 2004. p. 77-82 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Theocharides T, Link G, Swankoski E, Narayanan V, Irwin MJ, Schmit H. Evaluating alternative implementations for LDPC decoder check node function. In Smailagic A, Bayoumi M, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. 2004. p. 77-82. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339511