Evaluating the impact of architectural-level optimizations on clock power

D. Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin, Mahmut Kandemir

Research output: Contribution to journalConference article

5 Scopus citations

Abstract

A clock energy model is incorporated into a cycle-accurate energy simulator for an embedded architecture, which also resembles processor cores present in System-on-a-Chip (SoC) designs. This framework is used to study and quantify the influence on clock energy of several architectural-level decisions and their relative impact on the overall system energy. The design cases include various cache architectures and support for clock gating at different levels (global and local). At the software level, the influence on clock energy of power-oriented memory compiler optimizations is assessed.

Original languageEnglish (US)
Pages (from-to)447-451
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 2001
Event14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States
Duration: Sep 12 2001Sep 15 2001

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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