Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers

Rithika Shyam Chari, Tarek Elarabi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/ speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic Algorithm and 4 & 8-bit multipliers based on the Modified Booth Algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.

Original languageEnglish (US)
Title of host publicationProceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages243-248
Number of pages6
ISBN (Electronic)9781538614099
DOIs
Publication statusPublished - Jan 1 2017
Event11th UKSim-AMSS European Modelling Symposium on Computer Modelling and Simulation, EMS 2017 - Manchester, United Kingdom
Duration: Nov 20 2017Nov 22 2017

Publication series

NameProceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017

Other

Other11th UKSim-AMSS European Modelling Symposium on Computer Modelling and Simulation, EMS 2017
CountryUnited Kingdom
CityManchester
Period11/20/1711/22/17

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All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Computer Science Applications
  • Signal Processing
  • Modeling and Simulation

Cite this

Chari, R. S., & Elarabi, T. (2017). Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers. In Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017 (pp. 243-248). (Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EMS.2017.48