Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers

Rithika Shyam Chari, Tarek A. Elarabi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/ speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic Algorithm and 4 & 8-bit multipliers based on the Modified Booth Algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.

Original languageEnglish (US)
Title of host publicationProceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages243-248
Number of pages6
ISBN (Electronic)9781538614099
DOIs
StatePublished - May 9 2018
Event11th UKSim-AMSS European Modelling Symposium on Computer Modelling and Simulation, EMS 2017 - Manchester, United Kingdom
Duration: Nov 20 2017Nov 22 2017

Other

Other11th UKSim-AMSS European Modelling Symposium on Computer Modelling and Simulation, EMS 2017
CountryUnited Kingdom
CityManchester
Period11/20/1711/22/17

Fingerprint

Hardware Implementation
Multiplier
High Performance
Hardware
Computer hardware description languages
Computer architecture
Logic
Computer Architecture
Time delay
Error Rate
Time Delay
Minimise
Partial

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Computer Science Applications
  • Signal Processing
  • Modeling and Simulation

Cite this

Chari, R. S., & Elarabi, T. A. (2018). Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers. In Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017 (pp. 243-248). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EMS.2017.48
Chari, Rithika Shyam ; Elarabi, Tarek A. / Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers. Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 243-248
@inproceedings{e2b5925cb9ad4359abdd45c33975d260,
title = "Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers",
abstract = "The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/ speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic Algorithm and 4 & 8-bit multipliers based on the Modified Booth Algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.",
author = "Chari, {Rithika Shyam} and Elarabi, {Tarek A.}",
year = "2018",
month = "5",
day = "9",
doi = "10.1109/EMS.2017.48",
language = "English (US)",
pages = "243--248",
booktitle = "Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

Chari, RS & Elarabi, TA 2018, Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers. in Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017. Institute of Electrical and Electronics Engineers Inc., pp. 243-248, 11th UKSim-AMSS European Modelling Symposium on Computer Modelling and Simulation, EMS 2017, Manchester, United Kingdom, 11/20/17. https://doi.org/10.1109/EMS.2017.48

Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers. / Chari, Rithika Shyam; Elarabi, Tarek A.

Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 243-248.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers

AU - Chari, Rithika Shyam

AU - Elarabi, Tarek A.

PY - 2018/5/9

Y1 - 2018/5/9

N2 - The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/ speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic Algorithm and 4 & 8-bit multipliers based on the Modified Booth Algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.

AB - The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/ speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic Algorithm and 4 & 8-bit multipliers based on the Modified Booth Algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.

UR - http://www.scopus.com/inward/record.url?scp=85048366927&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048366927&partnerID=8YFLogxK

U2 - 10.1109/EMS.2017.48

DO - 10.1109/EMS.2017.48

M3 - Conference contribution

AN - SCOPUS:85048366927

SP - 243

EP - 248

BT - Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Chari RS, Elarabi TA. Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers. In Proceedings - UKSim-AMSS 11th European Modelling Symposium on Computer Modelling and Simulation, EMS 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 243-248 https://doi.org/10.1109/EMS.2017.48