TY - GEN
T1 - Excellent resistive switching characteristics of Cu doped ZrO2 and its 64 bit cross-point integration
AU - Liu, Ming
AU - Guan, Weihua
AU - Long, Shibing
AU - Liu, Qi
AU - Wang, Wei
PY - 2008/12/1
Y1 - 2008/12/1
N2 - Excellent nonpolar resistive switching behavior is reported in the Cu doped ZrO2 memory devices with the sandwiched structure of Cu/ZrO 2:Cu/Pt. The ratio between the high and low resistance is in the order of 106. Set and Reset operation in voltage pulse mode can be as fast as 50 ns and 100 ns, respectively. Multilevel storage is considered feasible due to the dependence of ON-state resistance on Set compliance current. The switching mechanism is demonstrated to be related with the formation and rupture of Cu conductive bridge. Based on this working cell, 64 bit cross-point array is fabricated and tested.
AB - Excellent nonpolar resistive switching behavior is reported in the Cu doped ZrO2 memory devices with the sandwiched structure of Cu/ZrO 2:Cu/Pt. The ratio between the high and low resistance is in the order of 106. Set and Reset operation in voltage pulse mode can be as fast as 50 ns and 100 ns, respectively. Multilevel storage is considered feasible due to the dependence of ON-state resistance on Set compliance current. The switching mechanism is demonstrated to be related with the formation and rupture of Cu conductive bridge. Based on this working cell, 64 bit cross-point array is fabricated and tested.
UR - http://www.scopus.com/inward/record.url?scp=60649099619&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=60649099619&partnerID=8YFLogxK
U2 - 10.1109/ICSICT.2008.4734692
DO - 10.1109/ICSICT.2008.4734692
M3 - Conference contribution
AN - SCOPUS:60649099619
SN - 9781424421855
T3 - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
SP - 905
EP - 908
BT - ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
T2 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Y2 - 20 October 2008 through 23 October 2008
ER -