Experimental evaluation of a compiler-based cache energy optimization strategy

Mahmut Kandemir, I. Kolcu, I. Kadayif

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present experimental results from an optimization strategy that aims at reducing per access energy cost for direct-mapped data caches. We have developed a compiler algorithm that uses access pattern analysis to determine those references that are certain to result in cache hits (called 'certain hits') in a virtually-addressed, direct-mapped data cache. After detecting such references, the compiler substitutes the corresponding load operations with 'energy-efficient loads' that access only data array of cache instead of both tag and data arrays. This tag access elimination, in turn, reduces the per access energy consumption for data accesses. Our experimental results indicate that certain hits constitute a large percentage of total hits. They also show that even our most conservative strategy improves the data cache energy consumption by 11% on the average.

Original languageEnglish (US)
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages296-300
Number of pages5
ISBN (Electronic)0780374940
DOIs
StatePublished - Jan 1 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
CountryUnited States
CityRochester
Period9/25/029/28/02

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Energy utilization
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kandemir, M., Kolcu, I., & Kadayif, I. (2002). Experimental evaluation of a compiler-based cache energy optimization strategy. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 296-300). [1158074] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158074
Kandemir, Mahmut ; Kolcu, I. ; Kadayif, I. / Experimental evaluation of a compiler-based cache energy optimization strategy. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 296-300 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).
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Kandemir, M, Kolcu, I & Kadayif, I 2002, Experimental evaluation of a compiler-based cache energy optimization strategy. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158074, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 296-300, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158074

Experimental evaluation of a compiler-based cache energy optimization strategy. / Kandemir, Mahmut; Kolcu, I.; Kadayif, I.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 296-300 1158074 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Kandemir M, Kolcu I, Kadayif I. Experimental evaluation of a compiler-based cache energy optimization strategy. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 296-300. 1158074. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). https://doi.org/10.1109/ASIC.2002.1158074