EXPERIMENTAL HARDWARE REALIZATION OF A MULTIPLE MICROPROCESSOR RESIDUE NUMBER DIGITAL FILTER.

R. Wolenty, William Kenneth Jenkins

    Research output: Contribution to journalConference article

    Abstract

    A digital filter structure was previously published that combines the combinatorial ROM technique of Peded and Liu with a residue number system architecture. This hybrid structure is suitable for multiple microprocessor realization because it requires no general multiplication and has a modularized structure due to the residue coding. This paper presents results from an experimental hardware realization of a second order elliptic filter using two microprocessors to realize this hybrid architecture.

    Original languageEnglish (US)
    Pages (from-to)1097-1100
    Number of pages4
    JournalProceedings - IEEE International Symposium on Circuits and Systems
    Volume3
    StatePublished - Jan 1 1980
    EventUnknown conference - Houston, TX, USA
    Duration: Apr 28 1980Apr 30 1980

    Fingerprint

    Digital filters
    Microprocessor chips
    Elliptic filters
    Hardware
    Numbering systems
    ROM

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering

    Cite this

    @article{2b012799d8564f6db1578dc2907bf67d,
    title = "EXPERIMENTAL HARDWARE REALIZATION OF A MULTIPLE MICROPROCESSOR RESIDUE NUMBER DIGITAL FILTER.",
    abstract = "A digital filter structure was previously published that combines the combinatorial ROM technique of Peded and Liu with a residue number system architecture. This hybrid structure is suitable for multiple microprocessor realization because it requires no general multiplication and has a modularized structure due to the residue coding. This paper presents results from an experimental hardware realization of a second order elliptic filter using two microprocessors to realize this hybrid architecture.",
    author = "R. Wolenty and Jenkins, {William Kenneth}",
    year = "1980",
    month = "1",
    day = "1",
    language = "English (US)",
    volume = "3",
    pages = "1097--1100",
    journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
    issn = "0271-4310",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",

    }

    EXPERIMENTAL HARDWARE REALIZATION OF A MULTIPLE MICROPROCESSOR RESIDUE NUMBER DIGITAL FILTER. / Wolenty, R.; Jenkins, William Kenneth.

    In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, 01.01.1980, p. 1097-1100.

    Research output: Contribution to journalConference article

    TY - JOUR

    T1 - EXPERIMENTAL HARDWARE REALIZATION OF A MULTIPLE MICROPROCESSOR RESIDUE NUMBER DIGITAL FILTER.

    AU - Wolenty, R.

    AU - Jenkins, William Kenneth

    PY - 1980/1/1

    Y1 - 1980/1/1

    N2 - A digital filter structure was previously published that combines the combinatorial ROM technique of Peded and Liu with a residue number system architecture. This hybrid structure is suitable for multiple microprocessor realization because it requires no general multiplication and has a modularized structure due to the residue coding. This paper presents results from an experimental hardware realization of a second order elliptic filter using two microprocessors to realize this hybrid architecture.

    AB - A digital filter structure was previously published that combines the combinatorial ROM technique of Peded and Liu with a residue number system architecture. This hybrid structure is suitable for multiple microprocessor realization because it requires no general multiplication and has a modularized structure due to the residue coding. This paper presents results from an experimental hardware realization of a second order elliptic filter using two microprocessors to realize this hybrid architecture.

    UR - http://www.scopus.com/inward/record.url?scp=0019281685&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0019281685&partnerID=8YFLogxK

    M3 - Conference article

    AN - SCOPUS:0019281685

    VL - 3

    SP - 1097

    EP - 1100

    JO - Proceedings - IEEE International Symposium on Circuits and Systems

    JF - Proceedings - IEEE International Symposium on Circuits and Systems

    SN - 0271-4310

    ER -