Exploiting barriers to optimize power consumption of CMPs

Chun Liu, Anand Sivasubramaniam, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Scopus citations

Abstract

Power consumption is an important concern for future billion transistor designs. This paper proposes a novel technique for optimizing the power consumption of chip-multiprocessors (CMPs) using an integrated hardware-software mechanism. By using a high level synchronization construct, called the barrier, our technique tracks the idle times spent by a processor waiting for other processors to get to the same point in the program. Using this knowledge, the frequency of the processors can be modulated to reduce/eliminate these idle times, thus providing power savings without compromising on performance. Using real applications from the SpecOMP suite, and a complete system CMP simulator, we demonstrate that this approach can provide as much as 40% power savings (and 32% on the average across five applications) with little impact on performance.

Original languageEnglish (US)
Title of host publicationProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Pages5a
DOIs
StatePublished - 2005
Event19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States
Duration: Apr 4 2005Apr 8 2005

Publication series

NameProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Volume2005

Other

Other19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
CountryUnited States
CityDenver, CO
Period4/4/054/8/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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