Exploiting clock skew scheduling for FPGA

Sungmin Bae, Prasanth Mangalagiri, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain design structural constraints that limit the CSS. In this paper, we present an analysis of several design structural constraints that affect the CSS and propose techniques to resolve these constraints. Furthermore, we propose a CSS FPGA architecture and a novel clock-period optimization (CPO) flow that tackles some of these constraints by exploiting the reconfigurability of FPGAs. Experimental results demonstrate that the proposed FPGA architecture with the CPO flow achieved an average performance improvement of 24.4% which was an average performance improvement of 10.7% over the CPO flow without considering the constraints.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Pages1524-1529
Number of pages6
StatePublished - Oct 22 2009
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: Apr 20 2009Apr 24 2009

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CountryFrance
CityNice
Period4/20/094/24/09

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Bae, S., Mangalagiri, P., & Vijaykrishnan, N. (2009). Exploiting clock skew scheduling for FPGA. In Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (pp. 1524-1529). [5090904] (Proceedings -Design, Automation and Test in Europe, DATE).