A multilevel logic synthesis technique based on minimizing communication complexity is presented. Intuitively, this approach is believed viable because for many types of circuits the area needed is dominated by interconnections. By minimizing communication complexity and interconnect, thus area is reduced. This approach performs especially well for functions that are hierarchically decomposable (e.g., adders, parity generators, comparators, etc.). Unlike many other multilevel logic synthesis techniques, a lower bound can be computed to determine how well the synthesis was performed. Also presented is a new multilevel logic synthesis program based on the techniques described for reducing communication complexity.
|Original language||English (US)|
|Number of pages||11|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Oct 1990|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering