Exploiting Communication Complexity for Multilevel Logic Synthesis

Ting Ting Hwang, Robert Michael Owens, Mary Jane Irwin

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

A multilevel logic synthesis technique based on minimizing communication complexity is presented. Intuitively, this approach is believed viable because for many types of circuits the area needed is dominated by interconnections. By minimizing communication complexity and interconnect, thus area is reduced. This approach performs especially well for functions that are hierarchically decomposable (e.g., adders, parity generators, comparators, etc.). Unlike many other multilevel logic synthesis techniques, a lower bound can be computed to determine how well the synthesis was performed. Also presented is a new multilevel logic synthesis program based on the techniques described for reducing communication complexity.

Original languageEnglish (US)
Pages (from-to)1017-1027
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume9
Issue number10
DOIs
StatePublished - Oct 1990

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Communication
Adders
Networks (circuits)
Logic Synthesis

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Hwang, Ting Ting ; Owens, Robert Michael ; Irwin, Mary Jane. / Exploiting Communication Complexity for Multilevel Logic Synthesis. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1990 ; Vol. 9, No. 10. pp. 1017-1027.
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Exploiting Communication Complexity for Multilevel Logic Synthesis. / Hwang, Ting Ting; Owens, Robert Michael; Irwin, Mary Jane.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 10, 10.1990, p. 1017-1027.

Research output: Contribution to journalArticle

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