Exploiting fine-grained data parallelism with chip multiprocessors and fast barriers

John Morgan Sampson, Rubén González, Jean Francois Collard, Norman P. Jouppi, Mike Schlansker, Brad Calder

Research output: Chapter in Book/Report/Conference proceedingConference contribution

40 Scopus citations

Abstract

We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vector machines. Parallelizing code in this manner leads to a high frequency of barriers, and we explore the impact of different barrier mechanisms upon the efficiency of this approach. To further exploit the potential of CMPs for fine-grained data parallel tasks, we present barrier filters, a mechanism for fast barrier synchronization on chip multi-processors to enable vector computations to be efficiently distributed across the cores of a CMP. We ensure that all threads arriving at a barrier require an unavailable cache line to proceed, and, by placing additional hardware in the shared portions of the memory subsytem, we starve their requests until they all have arrived. Specifically, our approach uses invalidation requests to both make cache lines unavailable and identify when a thread has reached the barrier. We examine two types of barrier filters, one synchronizing through instruction cache lines, and the other through data cache lines.

Original languageEnglish (US)
Title of host publicationProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
Pages235-246
Number of pages12
DOIs
StatePublished - Dec 1 2006
Event39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39 - Orlando, FL, United States
Duration: Dec 9 2006Dec 13 2006

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
CountryUnited States
CityOrlando, FL
Period12/9/0612/13/06

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Sampson, J. M., González, R., Collard, J. F., Jouppi, N. P., Schlansker, M., & Calder, B. (2006). Exploiting fine-grained data parallelism with chip multiprocessors and fast barriers. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39 (pp. 235-246). [4041850] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2006.23