Leakage energy optimization for caches has been the target of much recent effort. In this work, we focus on instruction caches and tailor two techniques that exploit the two major factors that shape the instruction access behavior, namely, hotspot execution and sequentiality. First, we adopt a hotspot detection mechanism by profiling the branch behavior at runtime and utilize this to implement a HotSpot based Leakage Management (HSLM) mechanism. Second, we exploit code sequentiality in implementing a Just-In-Time Activation (JITA) that transitions cache lines to active mode just before they are accessed. We utilize the recently proposed drowsy cache that dynamically scales voltages for leakage reduction and implement various schemes that use different combinations of HSLM and JITA. Our experimental evaluation using the SPEC2000 benchmark suite shows that instruction cache leakage energy consumption can be reduced by 63%, 49% and 29%, on the average, as compared to an unoptimized cache, a recently proposed hardware optimized cache, and a cache optimized using compiler, respectively. Further, we observe that these energy savings can be obtained without a significant impact on performance.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings of the International Symposium on Low Power Electronics and Design|
|State||Published - Dec 1 2003|
|Event||Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of|
Duration: Aug 25 2003 → Aug 27 2003
All Science Journal Classification (ASJC) codes