Effective utilization of on-chip storage space is important from both performance (execution cycles) and memory system energy consumptions perspectives. While on-chip cache memories have been widely used in the past, several factors, including lack of data access time predictability and limited effectiveness of compiler optimizations, indicate that they may not be the best candidate for portable/embedded devices. This paper presents a compiler-directed on-chip scratch-pad memory (software-managed on-chip memory) management strategy for data accesses. Our strategy is oriented towards minimizing the number of data transfers between off-chip memory and the scratch-pad memory, thereby exploiting reuse for the data residing in the scratch-pad memory. We report experimental data from our implementation showing the usefulness of our technique.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings of the International Symposium on System Synthesis|
|State||Published - 2001|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture