In many digital signal processing (DSP) applications, static random access memory (SRAM) based embedded memory and flip-flop based shift registers consume a significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory or flip-flop based shift registers are inefficient in terms of area and power. We propose spintronic domain wall memory (DWM) based embedded memories for DSP building blocks such as survivor-path memories and last-in first-out (LIFO) in Viterbi decoder, first-in-first-out (FIFO) register files in FFT processor and bitonic sorter, and input register of distributed arithmetic (DA) based FIR filter that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65 nm technology show that the DWM based design achieves significant area and power savings over the conventional SRAM and spin-transfer-torque RAM (STTRAM) based design approach. For 8 k-point FFT processor and Viterbi decoder, the DWM-based design shows 60.6% (8.4%) and 66.4% (-1.7%) area and 60.3% (44.3%) and 60.0% (37.8%) power savings over the conventional SRAM (STTRAM) based design, respectively. For DA-based FIR filter, it achieves 15.7% area and 15.5% power savings over shift register based design.
|Original language||English (US)|
|Number of pages||12|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Jan 1 2016|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering