Exploiting shared scratch pad memory space in embedded multiprocessor systems

Mahmut Kandemir, J. Ramanujam, A. Choudhary

Research output: Contribution to journalArticle

59 Scopus citations

Abstract

In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors. Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and 24.3% on average) on a four-processor embedded system. The results also show that the proposed strategy is robust in the sense that it gives consistently good results over a wide range of several architectural parameters.

Original languageEnglish (US)
Pages (from-to)219-224
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - Jan 1 2002

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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