Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte, Y. E. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Scopus citations

Abstract

The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period [5]. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual International Symposium on Microarchitecture
Pages102-113
Number of pages12
DOIs
StatePublished - Dec 1 2001
Event34th Annual International Symposium on Microarchitecture ACM/IEEE 2001 - Austin, TX, United States
Duration: Dec 1 2001Dec 5 2001

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture
ISSN (Print)1072-4451

Other

Other34th Annual International Symposium on Microarchitecture ACM/IEEE 2001
CountryUnited States
CityAustin, TX
Period12/1/0112/5/01

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

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